FPGA 20250611 LED

要背熟 要背熟 要背熟

module led_water(clk,led,reset_n);
input clk;
input reset_n;
output [7:0] led;

reg [7:0] led;
reg [23:0] counter;
reg [4:0] led_state;
reg clk_div;
// assign led = 8’h55;
always @(posedge clk)
begin
if(counter==24’hf00000)
begin
clk_div<=~clk_div;
counter<=24’h000000;
end
else
counter<=counter+1’b1;
end

always @(posedge clk_div or negedge reset_n)
begin
if(!reset_n)
begin
led<=8’hff;
led_state<=5’b0;
end
else
begin
case (led_state)
5’b00000: led<=8’b1111_1110;
5’b00001: led<=8’b1111_1101;
5’b00010: led<=8’b1111_1011;
5’b00011: led<=8’b1111_0111;
5’b00100: led<=8’b1110_1111;
5’b00101: led<=8’b1101_1111;
5’b00110: led<=8’b1011_1111;
5’b00111: led<=8’b0111_1111;

    5'b01000: led<=8'b1011_1111;
    5'b01001: led<=8'b1101_1111;
    5'b01010: led<=8'b1110_1111;
    5'b01011: led<=8'b1111_0111;
    5'b01100: led<=8'b1111_1011; 
    5'b01101: led<=8'b1111_1101; 
    5'b01110: led<=8'b1111_1110;

    5'b01111: led<=8'b1110_0111;
    5'b10000: led<=8'b1101_1011;
    5'b10001: led<=8'b1011_1101;
    5'b10010: led<=8'b0111_1110;

    5'b10011: led<=8'b1011_1101;
    5'b10100: led<=8'b1101_1011;
    5'b10101: led<=8'b1110_0111;

    5'b10110: led<=8'b1010_1010;
    5'b10111: led<=8'b0101_0101;

    5'b11000: led<=8'b1000_0000;
    5'b11001: led<=8'b0100_0000;
    5'b11010: led<=8'b0010_0000;
    5'b11011: led<=8'b0001_0000;
    5'b11100: led<=8'b0000_1000;
    5'b11101: led<=8'b0000_0100;
    5'b11110: led<=8'b0000_0010;
    5'b11111: led<=8'b0000_0001;
    default:led<=8'b1111_1111;
  endcase
 led_state<=led_state+1'b1;
end 

end
endmodule